1. Related Applications and Patents
U.S. patent application Ser. No. 11/621,357 (filed on Jan. 9, 2007) which is entitled “BROADBAND LOW NOISE COMPLEX REGENERATIVE FREQUENCY DIVIDERS” and Ser. No. 11/737,384 (filed on Apr. 19, 2007) which is entitled “BROADBAND LOW NOISE COMPLEX FREQUENCY MULTIPLIERS” are herein incorporated by reference. U.S. Patent Publication No. 20060057996 entitled “High frequency low noise phase-frequency detector and phase noise reduction method and apparatus” and U.S. Pat. No. 6,977,556 entitled “Rational frequency synthesizers” are also related to the subject matter and are herein incorporated by reference as well.
2. Field of the Invention
This invention relates to a device for performing frequency multiplication which exhibits low phase noise and low broadband noise. More particularly, the present invention employs integer, fractional and/or rational multiplication by using an array of Complex Frequency Shifters (CFS's) in combination with signal routing.
3. Background of the Related Art
Frequency multipliers along with frequency dividers are among the very essential building blocks in frequency generation and synthesis devices and are extensively used in these and many other applications. Signal sources with very low phase noise are increasingly more in demand as the frequencies utilized by such devices continue to increase along with the overall performance requirements. For example, the jitter of the clock caused by phase noise and broadband noise limits the achievable signal-to-noise ratio “SNR” in high speed ADCs/DACs. Reducing the clock jitter improves the achievable performance and allows higher frequency operation in demanding applications. This is one example among many where a low noise frequency multiplier allows for improved operating performance.
Numerous types of frequency multipliers are known in the art (e.g., frequency doublers), and include both analog and digital based devices. Generally speaking, analog multipliers have some advantages over digital multipliers in that they can operate at higher frequencies, achieve higher multiplication ratios, have lower phase noise and lower broadband noise, and consume less power. Analog multipliers can typically be divided in two categories: direct analog multipliers and the multipliers based on multiplying phase-lock loops or other schemes employing closed loop feedback systems or injection-locking mechanisms. As explained in detail below, the present invention falls within the category of direct analog multipliers.
Direct analog multipliers can further be divided into multipliers based on parametric nonlinearities of components, for instance nonlinear conductance or capacitive reactance and those using multiplying devices, such as mixers. Discrete circuits using nonlinearities of components such as diodes or transistors have been extensively used in the prior art, but typically need to be tuned to a specific frequency range or spectral component and are narrow-band. Mixer-based multipliers are a more systematic way of performing frequency multiplication, and provide wider bandwidth capabilities and have potential for larger multiplication ratios.
While devices for performing frequency multiplication by factorial of two (2) (for instance 2, 4, 8 . . . ) have been addressed in the prior art, that is not the case for frequency multiplication by an arbitrary integer factors. Also, generally speaking, devices for performing frequency multiplication by fractional or rational factor have not been addressed in the prior art. Further, the prior art fails to provide the rational frequency multiplier and synthesizer with low phase and broadband noise. Thus, there remains a need for a frequency multiplication device which provides for multiplication by integer, fractional and/or rational factors, which exhibits improved SNR and addresses the other limitations of the prior art devices noted above.